ML696201 and ML69Q6203
Preliminary
Pin Descriptions (Continued)
Primary/
Symbol
I/O
I
Description
Secondary
UP_RXD
UP_TXD
IDE
µPLAT SIO (UART) receive data
µPLAT SIO (UART) transmit data
Secondary
Secondary
O
IDEA [2:0]
O
I/O
O
O
I
IDE controller address
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
IDED [15:0]
IDERE_N
IDEWR_N
IDERDY
IDE controller data
IDE controller read enable, Active-Low
IDE controller write enable, Active-Low
This allows the IDE controller's I/O cycle extension.
Reset signal, Active-Low
IDERST_N
IDECS1_N
IDECS0_N
IDEDREQ
IDEDACK_N
IDEIRQ
O
O
O
I
IDE controller status/control select signal, Active-Low
IDE controller data/command select signal, Active-Low
IDE controller DMA request
O
I
IDE controller, DMA acknowledge, Active-Low
IDE controller interrupt input
IDENPCBRID
Flash
I
This detects the IDE primary cable ID.
FD[7:0]
I/O
O
O
I
NAND Flash data
Primary
Primary
Primary
Primary
Primary
Primary
FRD_N
NAND Flash read enable, Active-Low
NAND Flash write enable, Active-Low
NAND Flash ready/busy (1 = ready, 0 = busy)
NAND Flash address latch enable
NAND Flash command latch enable
FWR_N
FRB
FALE
O
O
FCLE
USB
USB_DP
I/O
I/O
I
USB DP input/output
USB DM input/output
USB REXT pin
Primary
Primary
Primary
Primary
Primary
USB_DM
USB_REXT
USB_VOREF
USB_ATEST [1:0]
I2S Reception
ICLKOUTA/CLKOUT
O
VoRef pin for USB TEST
USB ANALOG TEST pin 1-0
O
O
I2S receive system clock
Secondary
SDA
I
I2S receive data
I2S receive channel select
I2S receive transfer clock
Secondary
Secondary
Secondary
WSA
I/O
I/O
SCLA/SCL
I2S Transmission
CKOUTD
SDD
O
O
I2S transmit system clock
I2S transmit data
I2S transmit channel select
I2S transmit transfer clock
Secondary
Secondary
Secondary
Secondary
WSD
I/O
I/O
SCLD
I2C
SDAT
I/O
O
I2C transmit/receive data
I2C clock output
Primary
Primary
SCL
SSIO
SSIOCK [1:0]
I/O
SSIO clock pins 0 and 1
Secondary
10 • Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
