FEDL674001-01
OKI Semiconductor
ML674001/67Q4002/67Q4003
PIN DESCRIPTION
Primary/
I/O
Pin Name
Description
Logic
Secondary
System
RESET_N
BSEL[1:0]
I
I
Reset input
Negative
Positive
—
Boot device select signal
BSEL[1] BSEL[0]
Boot device
0
0
1
0
1
*
Internal Flash (External ROM for ML674001)
—
External ROM
Boot mode
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF)
after reset.
OSC0
I
Crystal connection or external clock input.
Connect a crystal (16 MHz to 33 MHz), if used, to OSC0 and OSC1_N.
It is also possible to input a direct clock.
—
—
—
—
OSC1_N
O
Crystal connection.
When not using a crystal, leave this pin unconnected.
CKO
O
I
Clock out
—
—
—
CKOE_N
Clock out enable
Negative
Debugging support.
TCK
I
I
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally leave open.
—
—
—
—
—
—
TMS
nTRST
TDI
Positive
Negative
Positive
Positive
I
I
TDO
O
General-purpose I/O ports
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
I/O
I/O
I/O
I/O
General-purpose port.
Primary
Primary
Primary
Primary
Positive
Positive
Positive
Positive
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Note that enabling DRAM controller with DRAME_N inputs permanently
configures PIOD[7:0] for their secondary functions, making them
unavailable for use as port pins.
PIOE[9:0]
I/O
General-purpose port.
Primary
Positive
Not available for use as port pins when secondary functions are in use.
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OKI [ OKI ELECTRONIC COMPONETS ]
