FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin
LQFP BGA
Primary Function
Description
Secondary Function
Symbol
I/O
VDD I/O power supply
Symbol
I/O
—
—
—
—
—
—
—
—
—
—
—
—
O
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
L4
M3
N4
L5
VDD_IO
XA[10]
XA[11]
XA[12]
XA[13]
XA[14]
GND
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
External address output
External address output
External address output
External address output
External address output
M4
N5
K5
M5
N6
M6
K6
L6
GND GND
XA[15]
XA[16]
XA[17]
GND
O
O
O
External address output
External address output
External address output
GND GND
XA[18]
PIOC[2]
VDD_IO
PIOC[3]
PIOC[4]
PIOC[5]
VDD_CORE
PIOC[6]
PIOC[7]
O
External address output
General port (with interrupt function)
M7
K7
L7
I/O
XA[19]
—
External address output
VDD I/O power supply
—
O
I/O
I/O
I/O
General port (with interrupt function)
XA[20]
XA[21]
XA[22]
—
External address output
External address output
External address output
N7
L8
General port (with interrupt function)
General port (with interrupt function)
O
O
K8
M8
M9
VDD CORE power supply
—
O
I/O
I/O
General port (with interrupt function)
XA[23]
XWR
External address output
General port (with interrupt function)
O
Transfer direction of
external bus
61
62
63
64
65
66
67
68
69
70
71
72
73
N8
K9
XOE_N
VDD_IO
O
Output enable (excluding SDRAM)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
VDD I/O power supply
M10 XWE_N
O
O
O
O
O
O
Write enable
N9
L9
XBWE_N[0]
Byte write enable (LSB)
Byte write enable (MSB)
External ROM chip select
External RAM chip select
IO chip select 0
XBWE_N[1]
XROMCS_N
L10
N10 XRAMCS_N
M11 XIOCS_N[0]
K10 GND
GND GND
N11 XIOCS_N[1]
M12 XIOCS_N[2]
N12 XIOCS_N[3]
N13 PIOD[6]
O
O
IO chip select 1
IO chip select 2
O
IO chip select 3
I/O
General port (with interrupt function)
XDQM[1]/XCAS
_N[1]
INPUT/OUTPUT
mask/CAS (MSB)
74
M13 PIOD[7]
I/O
General port (with interrupt function)
XDQM[0]/XCAS
_N[0]
O
INPUT/OUTPUT
mask/CAS (LSB)
75
76
L11
L13
PIOB[0]
PIOB[1]
I/O
I/O
General port (with interrupt function)
General port (with interrupt function)
DREQ[0]
I
DMA request signal (CH0)
DREQCLR[0]
O
DREQ Clear Signal
(CH0)
77
78
K11 VDD_IO
L12 PIOB[2]
VDD I/O power supply
I/O General port (with interrupt function)
—
—
I
DREQ[1]
DMA request signal
(CH1)
7/24
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