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ML67Q4002LA 参数 Datasheet PDF下载

ML67Q4002LA图片预览
型号: ML67Q4002LA
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 32-Bit, FLASH, 33.333MHz, CMOS, PBGA144, 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 19 页 / 645 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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ML674001/ML67Q4002/ML67Q4003  
Functional Description  
CPU  
Watch Dog Timer  
Functions as an interval timer or a watch dog timer.  
• 16-bit timer  
CPU core:  
ARM7TDMI  
Operating frequency:  
Instructions:  
1 MHz to 33 MHz (max)  
• Watch dog timer or interval timer mode can be selected  
• Interrupt reset generation  
ARM instruction (32-bit length) and Thumb  
instruction (16-bit length) can be mixed  
• Maximum period: longer than 200 msec  
General register bank: 31 x 32 bits  
Serial Interface  
This MCU contains four serial interfaces.  
1. SIO without FIFO: 1 channel  
Built-in barrel shifter:  
ALU and barrel shift operations can be executed  
by one instruction.  
Multiplier:  
32 bits x 8 bits (Modified Booth’s Algorithm)  
Built-in debug function: JTAG interface, break point register  
This is the serial port which performs data transmission, taking a synchro-  
nization per character.  
Selection of various parameters, such as addition of data length, a stop  
bit, and a parity bit, is possible.  
- Asynchronous full duplex operation  
- Sampling Rate = Baud rate x 16 samples  
- Character Length: 7, 8 bit  
- Stop Bit Length: 1, 2 bit  
- Parity: Even, Odd, none  
- Error Detection: Parity, Framing, Over run  
- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive  
addition  
Byte Ordering:  
Little Endian  
Built-in Memory  
FLASH ROM:  
ML674001 is the ROM-less version  
ML67Q4002: 256 KBytes (128K x 16 bits)  
ML67Q4003: 512 KBytes (256K x 16 bits)  
Access timing of this FLASH memory is configured by the  
ROM bank control register of the external memory  
controller.  
- Built-in Baud Rate Generator (8-bit counter) - Independent from a bus  
clock  
- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.  
SRAM: 32KB  
(8K x 32 bits)  
Read access (8/16/32 bit): 1 cycle  
Write access (32 bit): 1 cycle  
Write access (8/16 bit): 2 cycle  
2. UART with 16-byte FIFO: 1 channel  
Interrupt Controller  
Features 16-byte FIFO in both send and receive. Uses the industry stan-  
dard 16550A ACE (Asynchronous Communication Element).  
- Asynchronous full duplex operation  
- Reporting function for all status  
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter-  
rupt input signals. The interrupt controller controls these interrupt signals  
going to ARM core.  
- 16-Byte Transmit FIFO  
- 16-Byte Receive FIFO  
- Transmission, reception, interrupt of line status Data set and Indepen-  
dent FIFO control.  
- Modem control signals: CTS, DCD, DSR, DTR, RI and RTS  
- Data length: 5, 6, 7, or 8 bits  
1. Interrupt sources  
- FIQ: 1 external source (external pin: EFIQ_N)  
- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources  
(EXINT[3:0])  
2. Interrupt priority level  
- Configurable, 8-level priority for each source  
3. External interrupt pin input  
- Stop bit length: 1, 1.5, or 2 bits  
- parity: Even, Odd, or none  
- Error Detection: Parity, Framing, Overrun  
- Built-in Baud Rate Generation  
- EXINT[3:0] Can be set as Level or Edge sensing  
- Configurable High or Low when Level sensing. Configurable Rising- or  
Falling-edge triggering when Edge sensing. EFIQ_N is set as Falling-Edge  
triggering.  
3. Synchronous serial interface: 1 channel  
Clock-synchronous 8 bit serial port  
- selectable 1/8, 1/16 or 1/32 of the system clock frequency.  
- LSB First or MSB First.  
Timer  
Seven channels of 16-bit reload timers are employed. Of these, 1 channel is  
used as system timer for OS.  
- Master / Slave Mode  
- Transceiver buffer empty interrupt  
- Loopback Test Function  
The timers of other 6 channels are used in application software.  
2
1. System timer: 1 channel  
4. I C: 1 channel  
2
- 16-bit auto reload timer: Used as system timer for OS. Interrupt request  
by timer overflow.  
Based on the I C Bus specification. Operates as a single master device.  
- Communication mode: Master transmitter /master receiver  
- Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)  
- Addressing format: 7-bit / 10-bit  
- Data buffer: 1 Byte (1 step)  
- Communication Voltage: 2.7 V to 3.3 V  
2. Application timer: 6 channels  
- 16-bit auto reload timer  
- One shot, interval  
- Clock can be independently set for each channel  
April 2004, Rev 2.0  
Oki Semiconductor • 3  
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