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ML67Q4003TC 参数 Datasheet PDF下载

ML67Q4003TC图片预览
型号: ML67Q4003TC
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 32-Bit, FLASH, 33.333MHz, CMOS, PQFP144, 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144]
分类和应用: 微控制器
文件页数/大小: 19 页 / 645 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
 浏览型号ML67Q4003TC的Datasheet PDF文件第6页浏览型号ML67Q4003TC的Datasheet PDF文件第7页浏览型号ML67Q4003TC的Datasheet PDF文件第8页浏览型号ML67Q4003TC的Datasheet PDF文件第9页浏览型号ML67Q4003TC的Datasheet PDF文件第11页浏览型号ML67Q4003TC的Datasheet PDF文件第12页浏览型号ML67Q4003TC的Datasheet PDF文件第13页浏览型号ML67Q4003TC的Datasheet PDF文件第14页  
ML674001/ML67Q4002/ML67Q4003  
List of Pins (Continued)  
Pin  
Primary Function  
Secondary Function  
LQFP  
90  
BGA  
Symbol  
I/O  
Description  
Symbol  
I/O  
Description  
G10 GND  
GND  
GND  
91  
G11 VDD_IO  
G13 PIOD[2]  
F11 PIOD[3]  
F10 PIOD[4]  
F12 PIOD[5]  
E12 BSEL[0]  
F13 BSEL[1]  
E10 PIOE[5]  
D12 PIOE[6]  
E13 PIOE[7]  
E11 PIOE[8]  
D11 PIOE[9]  
D13 PIOE[0]  
C12 PIOE[1]  
D10 PIOE[2]  
C13 TDI  
VDD  
I/O power supply  
92  
I/O  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
Select boot device  
XRAS_N  
O
O
O
O
I
Row address strobe (SDRAM/EDO)  
Clock for SDRAM  
93  
I/O  
XSDCLK  
94  
I/O  
XSDCS_N  
Chip select for SDRAM  
Clock enable (SDRAM)  
95  
I/O  
XSDCKE  
96  
I
97  
I
Select boot device  
98  
I/O  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
General port (with interrupt function)  
JTAG Data Input  
EXINT[0]  
Interrupt input  
Interrupt input  
Interrupt input  
Interrupt input  
FIQ input  
99  
I/O  
EXINT[1]  
I
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
I/O  
EXINT[2]  
I
I/O  
EXINT[3]  
I
I/O  
EFIQ_N  
I
I/O  
SCLK  
SDI  
SDO  
I/O  
I
SSIO clock  
I/O  
SSIO Serial Data In  
SSIO Serial Data Out  
I/O  
O
I
I
B12 TDO  
O
JTAG data out  
B13 nTRST  
A13 NC  
I
JTAG reset, active Low  
NC  
A12 NC  
NC  
C11 CKO  
O
Clock output  
A11 JSEL  
I
JTAG select  
C10 TMS  
I
JTAG mode select  
B11 TCK  
I
JTAG clock  
A10 DRAME_N  
I
DRAM enable  
C9  
CKOE_N  
I
Clock out enable  
B10 GND  
GND  
GND  
A9  
D9  
B9  
A8  
B8  
D8  
C8  
B7  
D7  
C7  
A7  
C6  
D6  
B6  
B5  
A6  
D5  
OSC0  
I
Oscillation input pin  
OSC1_N  
VDD_IO  
TEST  
O
Oscillation output pin  
VDD  
IO power supply  
I
Test Mode  
PIOA[0]  
PIOA[1]  
AVDD  
VREF  
I/O  
General port (with interrupt function)  
General port (with interrupt function)  
A/D Converter power supply  
A/D Converter reference  
A/D Converter analog input port  
A/D Converter analog input port  
A/D Converter analog input port  
A/D Converter analog input port  
NC  
SIN  
SOUT  
UART Serial Data In  
UART Serial Data Out  
I/O  
O
VDD  
I
AIN[0]  
AIN[1]  
AIN[2]  
AIN[3]  
NC  
I
I
I
I
AGND  
GND  
GND  
GND  
I/O  
VDD  
GND for A/D Converter  
GND  
I
PIOA[2]  
VDD_IO  
General port (with interrupt function)  
IO power supply  
CTS  
UART Clear To Send  
10 • Oki Semiconductor  
April 2004, Rev 2.0