FEDL66525-02
OKI Semiconductor
ML66525 Family
(2) External data memory control
(VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C)
Parameter
Symbol
tcyc
Condition
fOSC = 24 MHz
Min.
41.67
Max.
—
Unit
Cycle time
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RDn pulse width
tφWH
tφWL
tRW
tWW
tRD
tWD
tAS
tAH
tRS
tRH
16.25
16.25
(2 + 2n)tφ – 25
(2 + 2n)tφ – 25
—
—
—
—
—
55
55
—
—
WRn pulse width
RDn pulse delay time
WRn pulse delay time
Address setup time
—
ns
CL = 50 pF
tφ – 20
tφ – 20
40
0
—
Address hold time
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
—
—
tACC
tWS
tWH
(3 + 2n)tφ – 50
2tφ – 30
tφ – 6
—
—
(Note) tφ = tcyc/2
n = 0 to 7 ( n wait cycles inserted)
tcyc
CPUCLK
RDn
tφWH
tφWL
tRW
RAP0 to 19
tRD
A0 to A19
tAS
tACC
tWD
tAS
tAH
DIN0 to 7
tRS
D0 to D7
WRn
tRH
tWW
RAP0 to 19
A0 to A19
D0 to D7
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
17/27
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