¡ Semiconductor
ML63512A/63514A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. The power to the circuits corresponding
to the signal names inside
is supplied from V
(power supply for interface).
DDI
nX-4/250
H
X
L
ROM
ML63512A: 4KW
ML63514A: 8KW
CBR
RA
PC
TIMING
CON-
TROL
Y
EBR
A
G
C
Z
SP
BUS
ALU
CON-
TROL
RSP
MIE
INSTRUCTION
DECODER
STACK
IR
CAL: 16-level
REG: 16-level
INT
2
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T0CK*
RAM
ML63512A: 128N
ML63514A: 256N
RESETB
RST
TIMER
8bit ¥ 2
T1CK*
INT
TST1B
TST2B
2
TST
RXC*
TXC*
RXD*
TXD*
INT
SIO
INT
1
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
MD
MELODY
OSC
INT
4
TBC
P0.0-P0.3
P1.0-P1.3
P2.0-P2.3
P3.0-P3.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3=
P9.0-P9.3=
PA.0-PA.3=
INT
1
LDIN0*
LDIN1*
Level
Detector
I/O
PORT
CMPIN*
CMPREF*
CMP
V
DDH
INT
4
V
DD
BACK-
UP
CB1
CB2
INPUT
PORT
P7.0-P7.3
P8.0-P8.3
V
VR
DDL
OUTPUT
PORT
V
V
DDI
SS
=
Port 6 (P6.0 to P6.3), Port 9 (P9.0 to P9.3) and Port A (PA.0 to PA.3) are only provided for the 64-
pin packages.
4/29
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