FEDL63295A-02
Semiconductor
1
ML63295A
BLOCK DIAGRAM
Asterisks (*) indicate the port secondary functions. Signal names enclosed by chain lines (
) indicate interface
signals of the V
DDI
power supply system. Signal names enclosed by
indicates signals of the V
DDE
power
supply system.
CPU core
TIMING
CONT.
SP
RSP
STACK
CAL.S:16-level
REG.S:16-level
ALU
MIE
INSTRUCTION
DECODER
IR
INT
2
CBR
EBR
H
X
nX-4/250
L
Y
C
RA
A
G
Z
BUS
CONT.
PC
ROM
32 KW
EXTMEM
64 KB
D0-7*
A0-15*
RD*
W R*
RAM
2048N
TIMER
8 bit (2ch)
T2CK*
T3CK*
RXC*
TXC*
RXD*
TXD*
SCLK*
SIN*
SOUT*
MD
MDB
P0.0-P0.3
P1.0-P1.3
P2.0-P2.3
P3.0-P3.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
INT
INT
2
SIO
INT
MULDIV
RESET
RST
TBC
DATA BUS
INT
TST1
TST2
TST
4
1
INT
1
SFT
MELODY
INT
1
INPUT
PORT
XT0
XT1
OSC0
OSC1
OSC
INT
1
INT
V
DDX1
V
DDX2
V
DDX3
V
DDX4
C1
C2
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
V
DD6
V
DD
V
DDL
V
DDE
1
BLD
100HzTC
OUTPUT
W DT
INT
BIAS
4
I/O
PORT
P8.0-P8.3
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PC.0-PC.3
PE.0-PE.3
LCD
&
DSPR
COM1-COM32
SEG0-SEG95
V
DDI
V
SS
VR
4/38
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