FEDL63187B-06
1Semiconductor
ML63187B/63189B
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
SCLK Input Fall Time
SCLK Input Rise Time
Symbol
Condition
Min.
—
Typ. Max. Unit
tf
tr
—
—
—
—
1.0
1.0
µs
µs
—
SCLK Input “L” Level
Pulse Width
tCWL
tCWH
—
—
0.8
0.8
—
—
—
—
µs
µs
SCLK Input “H” Level
Pulse Width
SCLK Input Cycle Time
tCYC
VDDI = 5 V to VDD
1.8
—
—
—
—
µs
µs
tCYC1(O)
CPU in operation state at 32.768 kHz
30.5
SCLK Output Cycle Time
CPU in operation at 2 MHz
VDD = VDDH = 1.8 to 3.5 V
tCYC2(O)
—
0.5
—
µs
SOUT Output Delay Time
SIN Input Setup Time
SIN Input Hold Time
tDDR
tDS
Output load capacitance 10 pF
—
—
—
—
0.4
—
µs
µs
µs
—
—
0.5
0.8
tDH
—
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
tCYC
5 V (VDDl
)
SCLK (PE.2)
0 V (VSS)
tr
tf
tCWH
tCWL
tDDR
tDDR
5 V (VDDI
)
SOUT (PE.1)
0 V (VSS)
tDS
tDS
tDH
5 V (VDDI
)
SIN (PE.0)
0 V (VSS)
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