FEDL63187B-06
1Semiconductor
ML63187B/63189B
PAD CONFIGURATION (ML63189B)
Pad Layout
62 SEG63
61 SEG62
60 SEG61
59 SEG60
58 SEG59
57 SEG58
56 SEG57
55 SEG56
54 SEG55
53 SEG54
52 SEG53
51 SEG52
50 SEG51
49 SEG50
48 SEG49
47 SEG48
46 SEG47
45 SEG46
44 SEG45
43 SEG44
42 SEG43
41 SEG42
40 SEG41
39 SEG40
38 SEG39
37 SEG38
36 SEG37
35 SEG36
34 SEG35
33 SEG34
32 SEG33
31 SEG32
VDDI 93
PE.0 94
PE.1 95
PE.2 96
PE.3 97
PB.0 98
PB.1 99
PB.2 100
PB.3 101
PA.0 102
PA.1 103
PA.2 104
PA.3 105
P9.0 106
P9.1 107
P9.2 108
P9.3 109
P0.0 110
P0.1 111
P0.2 112
P0.3 113
COM1 114
COM2 115
COM3 116
COM4 117
COM5 118
COM6 119
COM7 120
COM8 121
SEG0 122
SEG1 123
ML63189B
Y
X
(0,0)
Chip size
: 4.81 mm × 5.20 mm
Chip thickness
Coordinate origin
Pad hole size
Pad size
: 350 µm (280 µm: available as required)
: center of chip
: 100 µm × 100 µm
: 110 µm × 110 µm
Minimum pad pitch : 140 µm
Note: The chip substrate voltage is VSS.
11/36
OKI [ OKI ELECTRONIC COMPONETS ]
