PEDL60851C-02
1
Semiconductor
ML60851C
End Point 3 Data Toggle Register (EP3TGL)
Read address
Write address
F9h
79h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Sequence Toggle Bit
(R/Reset)
Data Sequence Toggle Bit: When initializing an EP, write a “1” in this bit to reset the toggle bit of the data packet
and specify PID of DATA0 (this bit also becomes “0”).
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.
End Point 3 Payload Register (EP3PLD)
Read address
Write address
FAh
7Ah
D7
0
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
After a hardware reset
After a bus reset
Definition
0
x
x
x
x
x
x
x
0
7-Bit general purpose register
This register can be used for any purpose. It is possible to retain or refer to the value written in this register without
affecting the other operations of the ML60851C. The initial values of bits other than D7 are indeterminate. Bit D7
is fixed at “0” and even if a “1” is written in this bit, it will be invalid.
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