PEDL60851C-02
1
Semiconductor
ML60851C
Interrupt Status Register (INTSTAT)
Read address
Write address
DCh
—
D7
0
See
below
D6
0
D5
D4
D3
0
D2
0
See
below
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
See
below below
0
See
0
0
0
0
Setup Ready Interrupt Status
EP1 Packet Ready Interrupt
Status
EP2 Packet Ready Interrupt
Status
EP0 Receive Packet Ready
Interrupt Status
EP0 Transmit Packet Ready
Interrupt Status
USB Bus Reset Interrupt Status
Suspend State Interrupt Status
EP3 Packet Ready Interrupt Status
Setup Ready Interrupt Status: When bit D0 of the interrupt enable register (INTENBL) is “1”, the content of bit
D0 of the EP0 status register (EP0STAT) is copied here.
This bit is “0” when D0 of INTENBL is “0”. In other words, when the eight bytes of setup
data are received in the setup stage of control transfer and are correctly stored in the setup
registers, this bit is set to “1” and the INTR pin is asserted.
EP1 Packet Ready Interrupt Status: When bit D1 of the interrupt enable register (INTENBL) is “1”, the negation of
the content of bit D1 or of bit D5 of the end point packet ready register (PKTRDY) is copied
here. This bit is “0” when bit D1 of INTENBL is “0”. The value at the time of a bus reset is
determined based on the value of INTENBL and the EP transfer direction at that time, and
also based on the value of the packet ready bit for that EP.
(If the EP1 transfer direction has been set as “Receive”, the negation of D1 is stored here, and
the negation of D5 is stored if the transfer direction has been set as “Transmit”.)
During data reception, the packet ready interrupt is generated when one packet of receive
data is correctly stored in one of the two FIFO layers of EP1. During transmission, the packet
ready interrupt is generated when data transmission has been completed from (and writing
becomes possible again) one of the two FIFO layers of EP1.
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