FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
Pin
Symbol
D6/SCK
Type
I/O
Description
Works as CPU interface data bus pin in parallel input interface.
Works as flash memory data output pin when reading the built-in flash
memory data.
When RD is at “L” level other than when reading the flash memory data,
this D6/SCK pin usually outputs “L” level.
24
26
Works as serial clock input pin in the serial input interface.
When the SCK input is at “L” level on the falling edge of CS, the DI input
is captured in device on the rising edge of SCK clock. And when the
SCK input is at “H” level on the falling edge of CS, the DI input is
captured on the falling edge of SCK clock.
Works as CPU interface data bus pin in the parallel input interface.
Works as flash data output pin when reading the built-in flash memory
data.
D7/DI
I/O
When RD is at “L” level at times other than reading the flash memory
data, this D7/DI pin usually outputs “L” level.
Works as serial data input pin in the serial input interface.
When OPTANA pin is at “H” level, this OUT(+)/DAO pin outputs PWM
(positive phase) of 1-bit DAC.
And when OPTANA pin is at “L” level, the OUT(+)/DAO pin outputs the
14-bit DAC analog signal.
28
29
OUT(+)/DAO
OUT(–)/AOUT
O
O
When OPTANA pin is at “H” level, this OUT(–)/AOUT pin outputs PWM
(reverse phase) of 1-bit DAC.
And when OPTANA pin is at “L” level, the OUT(–)/AOUT pin outputs the
14-bit DAC analog signal via voltage follower.
CPU interface switching pin.
At “H” level: Serial input interface. At “L” level: Parallel input interface.
CPU interface chip select pin.
32
36
SERIAL
I
I
CS
When CS pin is at “H” level, the WR, DW, and RD signals cannot be
input to the device.
Analog output/PWM output select signal.
At OPTANA pin = “H” level, PWM of 1-bit DAC is output from
OUT(+)/DAO and OUT(–)/AOUT pins.
At OPTANA pin = “L” level, 14-bit DAC analog signal is output from
OUT(+)/DAO pin and 14-bit DAC analog signal is output from
OUT(–)/AOUT pin via the voltage follower.
37
OPTANA
I
CPU interface write signal.
When CS pin is at “H” level, the WR signal cannot be input to the device.
Data write signal at EXT command and Flash I/F command.
When the EXT and Flash I/F commands are not used, keep this pin at
“H” level.
When CS pin is at “H” level, the DW signal cannot be input to the device.
This pin has a pull-up resistor built in.
42
2
WR
DW
I
I
CPU interface read signal.
This pin is used when reading the status signal of each channel or when
reading data of the built-in flash memory.
When not in use, keep this pin to “H” level.
This pin has a pull-up resistor built in.
Output pin for testing.
6
RD
I
7
8
TESTO
RD/BY
O
O
Keep this pin open.
Output pin to indicate the automatic erase/write status of the built-in
flash memory.
Outputs “L” level during erase or programming cycle to indicate the
busy state. Goes to “H” level at the end of the erase or programming
cycle and enters into the ready state.
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