FEDL2280XDIGEST-03
OKI Semiconductor
ML22808/ML22804/ML22802-XXX
FUNCTIONAL DESCRIPTION
Serial CPU Interface
Command data can be input through the DI pin by signals input through the CS and SCK pins.
Setting the CS pin to a “L” level enables the serial CPU interface.
After the CS pin is set to a “L” level, the command data, which is synchronized with the SCK clock signal, is
input through the DI pin from the MSB. The command data input through the DI pin is shifted into the LSI on
the rising or falling edges of the SCK clock pulses and the command is executed by the rising or falling edge of
the eighth pulse of the SCK clock.
Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by
the signal input through the DIPH pin:
- When the DIPH pin is at a “L” level, the data input through the DI pin is shifted into the LSI on the rising
edges of the SCK clock pulses.
- When the DIPH pin is at a “H” level, the data input through the DI pin is shifted into the LSI on the falling
edges of the SCK clock pulses.
It is possible to input command data in the LSI even by holding the CS pin continuously at a “L” level.
However, if unexpected pulses caused by noise are induced through the SCK pin, SCK clock pulses are
incorrectly counted. As a result, command data cannot be input correctly. Setting the CS pin to a “H” level
returns the count of the SCK clock pulses to the initial state.
11/18
OKI [ OKI ELECTRONIC COMPONETS ]
