FEDL2250DIGEST-09
OKI Semiconductor
ML2250 family
QFP
ML2256
WCSP pin
WCSP pin
Pin
Symbol
D6/SCK
Type
I/O
Description
CPU interface data bus pin in the parallel input interface.
Usually outputs “L” level when RD= “L” level.
Works as serial clock input pin in the serial input interface.
When the SCK input is at “L” level on the falling edge of WR,
RD, DW, the DI input is captured in the device on the rising
edge of SCK clock. And when the SCK input is at “H” level
on the falling edge of WR, RD, DW, the DI input is captured
on the falling edge of SCK clock.
24
F5
E6
CPU interface data bus pin in the parallel input interface.
26
C4
D5
D7/DI
I/O Usually output “L” level when RDis at “L” level.
Works as serial data input pin in the serial input interface.
28
29
F3
E3
E4
E3
DAO
O
O
DAO pin outputs analog signal of 14-bit DAC.
AOUT pin usually outputs the analog signal of 14-bit DAC
via voltage follower.
AOUT
CPU interface switching pin.
32
36
37
42
F1
D2
E1
C2
D2
D1
C2
B2
SERIAL
CS
I
I
I
I
Serial input interface at “H” level. And parallel input interface
at “L” level.
CPU interface chip select pin.
When CS pin is at “H” level, the WR, DW, and RD signals
cannot be input to the device.
Keep this pin “L” level. The analog signal of 14-bit DAC is
output from DAO pin and from AOUT pin via voltage
follower.
OPTANA
WR
CPU interface write signal.
When CSpin is at “H” level, the WRsignal cannot be input to
the device.
Data write signal when using EXT command for the voice
output.
Set the pin to “H” level when not using EXT command.
When CSpin is at “H” level, the DWsignal cannot be input to
the device.
This pin has a pull-up resistor built in.
CPU interface read signal.
2
6
B1
A3
C3
DW
I
I
When CSpin is at “H” level, the RDsignal cannot be input to
the device.
A4
RD
This pin has a pull-up resistor built in.
Output pin for testing.
Keep this pin open.
B4
C4
TESTO1
TESTO2
7, 8
30
B3, A4
F2
O
Analog power supply pin.
Insert a 0.1 F or larger bypass capacitor between this pin
and AGND pin.
E2
AVDD
DVDD
—
Digital power supply pin.
Insert a 0.1 F or larger bypass capacitor between this pin
and DGND pin.
13, 40
B5, C1
A6,B1
—
27
17, 31,
39
F4
C6, D1,
E2
E5
AGND
DGND
—
—
Analog ground pin.
C1,C7,E1
Digital ground pin.
13/36
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