FEDL2215-01
Semiconductor
ML2215
1
You must input the external clock to the CLK pin. Otherwise, serial data input cannot be acquired internally,
regardless tSDST ≥ 1 µs or tSDST < 1 µs.
tSDST
tSDST
SD
SI
NAR
BUSY
Figure 4.2 Timing Chart of Serial Input
As shown in Figure 4.2, re-inputting the Start-bit before the SI’s 8th clock cancels the preceding serial data entry,
and 8-clock data following the Start-bit is taken as valid data.
4.2 3-pin Controlled Serial Input Interface
3-pin interfacing uses the SD, SI and ST pins to control interfacing.
ST
SD
SI
NAR
BUSY
Figure 4.3 Timing Chart of Serial Input
When 3-pin interfacing is selected, input to the SD and SI pins is enabled while the ST pin being held “L”. Serial
data input to the SD pin is acquired to the internal register in synchronization with the falling edge of the SI’s 8th
clock as an 8-bit phrase code for a user-defined phrase. If the ST pin is brought back to “H” before the SI’s 8th
clock, the preceding entry is cancelled, and 8-clock data after the ST pin being brought back to “L” again is taken
as valid data.
13/26
OKI [ OKI ELECTRONIC COMPONETS ]
