MK32VT1672A-8YC (98.07.06)
SERIAL PRESENCE DETECT
Byte
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
SPD
Hex Value
80
08
04
0C
09
02
48
00
01
80
60
02
80
08
08
01
8F
04
06
01
01
00
0E
C0
A0
00
00
1E
10
14
30
10
20
10
20
10
00-00
12
5C
41,45,20,20,20,20,20,20
01 / 06
Remark
Defines the number of bytes written into
SPD memory
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
Number of columns
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
Cycle time (CL=3)
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Notes
128 byte
256 byte
SDRAM
12 rows
9 columns
2 bank
72 bits
0
LVTTL
CL=3 t
CC
=8ns
CL=3 t
AC3
=6ns
ECC
Normal / Self
x8
x8
t
CCD
: 1 CLK
1, 2, 4, 8, F
4 banks
2, 3
0
0
CL=2 t
CC2
=12ns
CL=2 t
AC2
=10ns
Not support
Not support
t
RP
=30ns
t
RRD
=16ns
t
RCD
=20ns
t
RAS
=48ns
64MB
Command and address signal input setup time
2ns
Command and address signal input hold time
1ns
Data signal input setup time
2ns
Data signal input hold time
1ns
R.F.U
SPD data revision code
1.2
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
MK32VT1672A-8YC
4D,4B,33,32,56,54,31,36,37,
32,41,2D,38,59,43,20,20,20
20, 20
91, 92
00-00
93-125
64
126
F5
127
FF-FF
128-255
Manufacturer’s part number
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
100MHz
CLK0-3, CL=3
OKI [ OKI ELECTRONIC COMPONETS ]
