MK31VT832-10YC 98.09.03
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Ò
SERIAL PRESENCE DETECT
Byte
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
SPD
Hex Value
80
08
04
0C
09
01
20
00
01
A0
90
00
80
08
00
01
0E
04
06
01
01
00
06
F0
90
00
00
1E
14
1E
3C
08
30
10
30
10
00-00
02
32
41,45,20,20,20,20,20,20
01 / 06
Remark
Defines the number of bytes written into
SPD memory
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
Number of columns
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
Cycle time (CL=3)
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
128 byte
Notes
256 byte
SDRAM
12 rows
9 columns
1 bank
32 bits
0
LVTTL
CL=3 t
CC3
=10ns
CL=3 t
AC3
=9ns
None Parity
Normal / Self
x8
t
CCD
: 1 CLK
2, 4, 8
4 banks
2, 3
0
0
CL=2 t
CC2
=15ns
CL=2 t
AC2
=9ns
Not support
Not support
t
RP
=30ns
t
RRD
=20ns
t
RCD
=30ns
t
RAS
=60ns
32MB
Command and address signal input setup time
3ns
Command and address signal input hold time
1ns
Data signal input setup time
3ns
Data signal input hold time
1ns
Superset Information
R.F.U
SPD data revision code
0.2
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
MK31VT832-10YC
4D,4B,33,31,56,54,38,33,32,
2D,31,30,59,43,20,20,20,20
20, 20
91, 92
00-00
93-125
66
126
06
127
FF-FF
128-255
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
66MHz
CL=2, 3
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