■ MG113P/114P/115P/73P/74P/75P ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Separate power bus (V
, V
) for
DDC
SSC
I/O base cells
internal core logic (2nd metal/3rd metal)
Configurable I/O pads
for V , V , or I/O
DD
SS
1, 2, 3, 4, or 5 layer
metal
interconnection in
core area
Core base cell
with 4 transistors
V
, V pads (4) in each
Separate power bus (V
, V
) over I/O cell
DD
SS
DDO
SSO
corner for wafer probing only
for output buffers (2nd metal/3rd metal)
Figure 7. MG115P Array Architecture
MG73P/74P/75P CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
-
-
Identify macrocell functions required and minimum array size to hold macrocell functions.
Add together all the area occupied by the required random logic and macrocells and select
the optimum array.
2. Make a floor plan for the design’s megacells.
-
-
Oki Design Center engineers verify the master slice and review simulation.
Oki Design Center or customer engineers floorplan the array using Oki’s supported floor-
planner or Cadence DP3 or Gambit GFP and customer performance specifications.
-
Using Oki CAD software, Design Center engineers remove the SOG transistors and replace
them with diffused memory macrocells to the customer’s specifications.
4
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