––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■
DC Characteristics (V Core = 2.25 to 2.75 V, V I/O = 2.25 to 2.75 V, V = 0 V, T = -40° to +125°C)
DD
DD
SS
j
Rated Value
[1]
Parameter
High-level input voltage
Symbol
VIH
Conditions
Min.
Typ.
Max.
Unit
TTL input (normal), VDD=VDD I/O
TTL input (normal)
1.7
-
VDD + 0.3
Low-level input voltage
VIL
Vt+
Vt-
-0.3
-
0.7
1.7
-
TTL- level Schmitt
Trigger input buffer
Threshold voltage
TTL input (normal)
-
-
0.6
-
∆Vt
VOH
Vt+ - Vt-
-
0.4
-
V
High-level output voltage (Output buffer)
Low-level output voltage (Output buffer)
IOH = -100 µA, VDD=VDD I/O
VDD - 0.2
-
-
I
OH = -0.5, -1, -2, -3, -4, -6, -12 mA
IOL = 100 µA
OL = -0.5, 1, 2, 3, 4, 6, 12 mA
1.95
-
-
-
VOL
-
0.2
0.45
50
50
-
I
-
-
High-level input current (Input buffer)
IIH
IIL
VIH = VDD
VIL = VSS
-50
-50
-
-
µA
mA
µA
Low-level input current (Normal input buffer)
-
-0.8
-
V
IL = VSS (3-kΩ pull-up)
3-state output leakage current
(Normal input buffer)
IOZH
IOZL
VOH = VDD
VOL = VSS
-50
-50
-
50
50
-
-
V
OL = VSS (3-kΩ pull-up)
-0.8
mA
µA
Stand-by current [2]
IDDQ
Output open, VIH = VDD, VIL = VSS
Design Dependent
1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25°C for a typical process.
2. RAM/ROM should be in powerdown mode.
Oki Semiconductor
9