■ KGL4217/KGL4221/KGL4222 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PACKAGE OUTLINE
17.41 SQ
15.57 SQ
12.00 SQ
0.7
0.5
0.645
1.845
48
37
1
36
Top View
12
25
13
24
0.125 ±0.05
Dimension in mm.
PIN CONFIGURATION
Pin No
1
Signal
G
Pin Definition
Ground
Pin No
Signal
D6
Pin Definition
Data input 6
Pin No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal
Pin Definition
Ground
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
G
G
2
LCKN
G
1/16 clock (neg)
Ground
G
Ground
Ground
3
VTT
D8
Power supply
Data input 8
Data input A
Data input C
Data input E
Power supply
Ground
G
Ground
4
LCKN
G
1/16 clock (pos)
Ground
G
Ground
5
DA
DC
DE
VTT
DF
DD
DB
D9
G
Power supply
Data input F
Data input D
Data input B
Data input 9
Ground
6
VTT
VTT
G
Power supply
Power supply
Ground
7
8
VTT
G
9
Q
Data output (pos)
Ground
10
11
12
13
14
15
16
G
HCR
G
Clock reference bias
Ground
QN
G
Data output (neg)
Ground
VTT
D7
D5
D3
D1
VTT
Power supply
Data input 7
Data input 5
Data input 3
Data input 1
Power supply
HCK
G
Clock input
Ground
VTT
D0
D2
D4
Power supply
Data input 0
Data input 2
Data input 4
VTT
VTT
G
Power supply
Power supply
Ground
10
Oki Semiconductor