■ KGL4217/KGL4221/KGL4222 ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PACKAGE OUTLINE
17.41 SQ
15.57 SQ
12.00 SQ
0.7
0.5
0.645
1.845
48
37
1
36
Top View
12
25
13
24
0.125 ±0.05
Dimension in mm.
PIN CONFIGURATION
Pin No
1
Signal
G
Pin Definition
Ground
Pin No
Signal
Q7
Pin Definition
Data input 7
Pin No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal
Pin Definition
Ground
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
G
G
2
LCKN
G
1/16 clock (neg)
Ground
G
Ground
Ground
3
VTT
Q9
Power supply
Data input 9
Data input B
Data input D
Data input F
Power supply
Ground
G
Ground
4
LCKN
G
1/16 clock (pos)
Ground
G
Ground
5
QB
QD
QF
VTT
QE
QC
QA
Q8
G
Power supply
Data input E
Data input C
Data output A
Data output 8
Ground
6
VTT
VTT
G
Power supply
Power supply
Ground
7
8
VTT
G
9
DAT
G
Data input
10
11
12
13
14
15
16
Ground
HCR
G
Clock reference bias
Ground
DAR
G
Data reference bias
Ground
VTT
Q6
Q4
Q2
Q0
VTT
Power supply
Data output 6
Data output 4
Data output 2
Data output 0
Power supply
HCK
G
Clock input
Ground
VTT
Q1
Power supply
Data output 1
Data output 3
Data output 5
VTT
VTT
G
Power supply
Power supply
Ground
Q3
Q5
14
Oki Semiconductor