TDA6650TT; TDA6651TT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
signal
source
LBIN
or
27 Ω
50 Ω
IFOUTA
spectrum
analyzer
MBIN
DUT
e
V
meas
50 Ω
V
50 Ω
IFOUTB
RMS
voltmeter
V
CCA
fce755
Zi >> 50 Ω → Vi = 2 × Vmeas
.
Vi = Vmeas + 6 dB.
Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical
IF output
signal
source
27 Ω
50 Ω
A
HBIN1
HBIN2
IFOUTA
IFOUTB
C
spectrum
analyzer
DUT
HYBRID
V
V
meas
50 Ω
V
50 Ω
e
i
B
D
50 Ω
RMS
voltmeter
V
CCA
fce756
Loss in hybrid = 1 dB.
Vi = Vmeas − loss.
Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output
12.1 PLL loop stability of measurement circuit
The TDA6650TT; TDA6651TT PLL loop stability is guaranteed in the configuration of
Figure 27, 28, 29 and 30. In this configuration, the external supply source is 30 V
minimum, the pull-up resistor R19 is 15 kΩ and all of the local oscillators are aligned to
operate at a maximum tuning voltage of 26 V. If the configuration is changed, there might
be an impact on the loop stability.
For any other configurations, a stability analysis must be performed. The conventional PLL
AC model used for the stability analysis, is valid provided the external source (DC supply
source or DC-to-DC converter) is able to deliver a minimum current that is equal to the
charge pump current in use.
TDA6650TT_6651TT_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 10 January 2007
39 of 54
NXP [ NXP ]
