Product specification
TDA4858
Fig.1 Block diagram and application circuit.
handbook, full pagewidth
1997 Oct 27
VPOS
VAMP
VSCOR
RVREF
CVAGC
39 kΩ
39 kΩ
VOUT1 VOUT2
19
13
12
17
18
39 kΩ
VREF
23
VCAP
24
VAGC
22
100
22
nF
kΩ
1% C
5%
VCAP
220 kΩ
220 kΩ
220 kΩ
100
nF
POLARITY
CORRECTION
VERTICAL
OSCILLATOR
AGC
VERTICAL POSITION
VERTICAL SIZE
VERTICAL
OUTPUT STAGE
S-CORRECTION
21 EWPAR 39 kΩ
220 kΩ
32 EWWID 39 kΩ
VERTICAL SYNC
INTEGRATOR
EW
PARABOLA
220 kΩ
20 EWTRP 39 kΩ
11
2
220 kΩ
EWDRV
EW
parabola
horizontal
size
EW
trapeziun
BLOCK DIAGRAM
Philips Semiconductors
VSYNC
(TTL level)
14
VERTICAL
SYNC
INPUT
9.2 to 16 V
9
VCC
PGND 8
SGND 25
SUPPLY
AND
REFERENCE
TDA4858
clamping
blanking
CLBL
16
VIDEO CLAMPING PULSE
VERTICAL BLANKING
XRAY
6 BDRV
4 BSENS
B+
CONTROL
3 BOP
5 BIN
Economy Autosync Deflection Controller
(EASDC)
4
FREQUENCY DETECTOR
COINCIDENCE DETECTOR
X-RAY
PROTECTION
POLARITY
CORRECTION
PLL1
PLL2
HORIZONTAL
OSCILLATOR
26
HPLL1
RHBUF
RHREF
(1)
(1)
10 nF
2%
HBUF
HREF
HCAP
27
30
28
29
31
HPLL2
HFLB
12 nF
HDRV
1
7
27 kΩ
47 nF
220
kΩ
1.5
nF
39
kΩ
HPOS
(2)
B+ CONTROL
APPLICATION
CLSEL 10
HSYNC
(TTL level) 15
HORIZONTAL/
COMPOSITE
SYNC INPUT
HORIZONTAL
OUTPUT
STAGE
(video)
MGD094
(1) For the calculation of f
H
range see Section “Calculation of line frequency range”.
(2) See Figs 12 and 13.
PHILIPS [ NXP SEMICONDUCTORS ]
