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7.7
Bit allocation map
Table 3 Slave receiver (slave address 88H or 8CH)
DATA BYTE(1)
D4 D3
REGISTER FUNCTION
Null
SUBADDR
D7
D6
D5
D2
D1
D0
00H to 25H
26H
0
0
0
0
0
0
0
0
Wide screen signal
Wide screen signal
Real-time control, burst start
Burst end
WSS7
WSS6
0
WSS5
WSS13
BS5
WSS4
WSS12
BS4
WSS3
WSS11
BS3
WSS2
WSS10
BS2
WSS1
WSS9
BS1
WSS0
WSS8
BS0
27H
WSSON
28H
DECCOL DECFIS
29H
0
0
BE5
BE4
BE3
BE2
BE1
BE0
Copy guard odd 0
Copy guard odd 1
Copy guard even 0
Copy guard even 1
Copy guard enable
Null
2AH
CGO07
CGO17
CGE07
CGE17
CGEN1
0
CGO06
CGO16
CGE06
CGE16
CGEN0
0
CGO05
CGO15
CGE05
CGE15
0
CGO04
CGO14
CGE04
CGE14
0
CGO03
CGO13
CGE03
CGE13
0
CGO02
CGO12
CGE02
CGE12
0
CGO01
CGO11
CGE01
CGE11
0
CGO00
CGO10
CGE00
CGE10
0
2BH
2CH
2DH
2EH
2FH to 39H
3AH
0
0
0
0
0
0
Input port control
Chrominance phase
Gain U
CBENB
CHPS7
GAINU7
GAINV7
GAINU8
0
0
SYMP
CHPS4
GAINU4
GAINV4
BLCKL4
0
0
Y2C
UV2C
CHPS0
GAINU0
GAINV0
BLCKL0
5AH
CHPS6
GAINU6
GAINV6
DECOE
CHPS5
GAINU5
GAINV5
BLCKL5
CHPS3
GAINU3
GAINV3
BLCKL3
CHPS2
GAINU2
GAINV2
BLCKL2
CHPS1
GAINU1
GAINV1
BLCKL1
5BH
Gain V
5CH
Gain U MSB, real-time control,
black level
5DH
Gain V MSB, real-time control,
blanking level
5EH
GAINV8
DECPH
BLNNL5
BLNNL4
BLNNL3
BLNNL2
BLNNL1
BLNNL0
CCR, blanking level VBI
Null
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
CCRS1
0
CCRS0
0
BLNVB5
0
BLNVB4
0
BLNVB3
0
BLNVB2
0
BLNVB1
0
BLNVB0
0
Standard control
RTC enable, burst amplitude
Subcarrier 0
0
DOWN
BSTA6
FSC06
FSC14
FSC22
FSC30
L21O06
L21O16
INPI
YGS
0
SCBW
BSTA2
FSC02
FSC10
FSC18
FSC26
L21O02
L21O12
PAL
FISE
RTCE
FSC07
FSC15
FSC23
FSC31
L21O07
L21O17
BSTA5
FSC05
FSC13
FSC21
FSC29
L21O05
L21O15
BSTA4
FSC04
FSC12
FSC20
FSC28
L21O04
L21O14
BSTA3
FSC03
FSC11
FSC19
FSC27
L21O03
L21O13
BSTA1
FSC01
FSC09
FSC17
FSC25
L21O01
L21O11
BSTA0
FSC00
FSC08
FSC16
FSC24
L21O00
L21O10
Subcarrier 1
Subcarrier 2
Subcarrier 3
Line 21 odd 0
Line 21 odd 1
NXP [ NXP ]
