欢迎访问ic37.com |
会员登录 免费注册
发布采购

PRTR5V0U2X 参数 Datasheet PDF下载

PRTR5V0U2X图片预览
型号: PRTR5V0U2X
PDF下载: 下载PDF文件 查看货源
内容描述: 在SOT143B超低电容双轨对轨ESD保护二极管 [Ultra low capacitance double rail-to-rail ESD protection diode in SOT143B]
分类和应用: 瞬态抑制器二极管光电二极管局域网
文件页数/大小: 10 页 / 59 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
 浏览型号PRTR5V0U2X的Datasheet PDF文件第2页浏览型号PRTR5V0U2X的Datasheet PDF文件第3页浏览型号PRTR5V0U2X的Datasheet PDF文件第4页浏览型号PRTR5V0U2X的Datasheet PDF文件第5页浏览型号PRTR5V0U2X的Datasheet PDF文件第7页浏览型号PRTR5V0U2X的Datasheet PDF文件第8页浏览型号PRTR5V0U2X的Datasheet PDF文件第9页浏览型号PRTR5V0U2X的Datasheet PDF文件第10页  
Philips Semiconductors
PRTR5V0U2X
Ultra low capacitance double rail-to-rail ESD protection diode
7. Application information
Handling data rates up to 480 Mbit/s, USB 2.0 interfaces require ESD protection devices
with an extremely low line capacitance in order to avoid signal distortion.
With a capacitance of only 1 pF, the Philips PRTR5V0U2X offers IEC 61000-4-2, level 4
compliant ESD protection.
The PRTR5V0U2X integrates two ultra-low capacitance rail-to-rail ESD protection diodes
and an additional ESD protection diode in a small 4 lead SOT143B package.
The additional ESD protection diode connected between ground and V
CC
prevents
charging of the supply.
To achieve the maximum ESD protection level, no additional external capacitors are
required.
USB controller
common mode
choke
D+
D−
V
BUS
protected IC/device
V
BUS
D+
D−
GND
006aaa485
Fig 5. Application diagram: USB 2.0
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PRTR5V0U2X as close to the input terminal or connector as possible.
2. The path length between the PRTR5V0U2X and the protected line should be
minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all printed-circuit board conductive loops including power and ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer printed-circuit
boards, use ground vias.
9397 750 15163
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 September 2005
6 of 10