PCF8563
NXP Semiconductors
Real-time clock/calendar
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
mba605
Fig 16. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 17.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 17. Acknowledgement on the I2C-bus
PCF8563
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 16 June 2011
22 of 45
NXP [ NXP ]
