Philips Semiconductors
Product data sheet
Parallel bus to I
2
C-bus controller
PCA9564
PIN CONFIGURATION — DIP, SO, TSSOP
D0
D1
D2
D3
D4
D5
D6
D7
DNU
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 RESET
16 INT
15 A1
PIN CONFIGURATION — HVQFN
16 SDA
15 SCL
14 RESET
13 INT
12 A1
11 A0
CE 10
6
7
8
WR
9
RD
17 V
DD
20 D2
19 D1
V
SS
18 D0
D3
D4
D5
D6
1
2
3
4
5
TOP VIEW
14 A0
13 CE
12 RD
11 WR
D7
V
SS
10
DNU
SW02260
SW02261
PIN DESCRIPTION
PIN NUMBER
DIP, SO, TSSOP
1, 2, 3, 4,
5, 6, 7, 8
9
10
11
HVQFN
1, 2, 3, 4, 5,
18, 19, 20
6
7
1
8
SYMBOL
D0–D7
DNU
V
SS
WR
Pwr
I
PIN
TYPE
I/O
NAME AND FUNCTION
Data Bus:
Bi-directional 3-State data bus used to transfer commands, data and
status between the controller and the CPU. D0 is the least significant bit.
Do not use: must be left floating (pulled LOW internally)
Ground
Write Strobe:
When LOW and CE is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
Read Strobe:
When LOW and CE is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RD.
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU
and the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1
inputs. When HIGH, places the D0–D7 lines in the 3-State condition.
Address Inputs:
Selects the controller internal registers and ports for read/write
operations.
Interrupt Request:
Active-LOW, open-drain, output. This pin requires a pull-up
device.
Reset:
A LOW level clears internal registers resets the I
2
C state machine.
I
2
C-bus serial clock input/output (open-drain).
I
2
C-bus serial data input/output (open-drain).
Power Supply:
2.3 to 3.6 V
12
9
RD
I
13
10
CE
I
14, 15
16
17
18
19
20
11, 12
13
14
15
16
17
A0, A1
INT
RESET
SCL
SDA
V
DD
I
O
I
I/O
I/O
Pwr
NOTES:
1. HVQFN package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be connected to supply ground for
proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board
using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in
the PCB in the thermal pad region.
2006 Sep 01
3
PHILIPS [ NXP SEMICONDUCTORS ]
