LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.23.2 SHA-1 and SHA-2
The Hash peripheral is used to perform SHA-1 and SHA-2 (256) based hashing. A hash
takes an arbitrarily large message or image and forms a relatively small fixed size
“unique” number called a digest. The data is fed by words from the processor, DMA, or
hosted access; the words are converted from little-endian (ARM standard) to big-endian
(SHA standard) by the block.
7.23.2.1 Features
• Used with an HMAC to support a challenge/response or to validate a message.
• Can be used to verify external memory that has not been compromised.
7.24 Code security (enhanced Code Read Protection - eCRP)
eCRP is a mechanism that allows the user to enable different features in the security
system. The features are specified using a combination of OTP and flash values. Some
levels are only controlled by either flash or OTP, but the majority have dual control. The
overlap allows higher security by specifying access using OTP bits, which cannot be
changed (except to increase security) while allowing customers who are less concerned
about security the ability to change levels in the flash image.
eCRP is calculated by reading the ECRP from the flash boot sector (offset 0x0000 0020)
and then masking it with the value read from OTP. The OTP bits are more restrictive (that
is, disable access) than equivalent values in flash. Certain aspects of eCRP are only
specified in the OTP (that is, Mass Erase disable), while others are only specified in flash
(that is, Sector Protection count).
For Dual Enhanced images, eCRP is calculated by reading the eCRP from the bootable
image sector. The bootable image is defined as the highest revision image that passes the
required validation methods.
7.25 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported. The ARM Cortex-M4 is configured to support up to eight
breakpoints and four watch points.
The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,
execute the boot code, restart from address 0x0000 0000, and break at the user entry
point.
The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the
SWD functions by default.
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
82 of 169
NXP [ NXP ]
