LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.18.3.1 Features
• Read and write buffers to reduce latency and to improve performance.
• Low transaction latency.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• 8/16/32 data and 16/20/26 address lines wide static memory support.
• Static memory features include:
– Asynchronous page mode read.
– Programmable Wait States.
– Bus turnaround delay.
– Output enable and write enable delays.
– Extended wait.
• Dynamic memory interface support including single data rate SDRAM.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• EMC bus width (bit) on LQFP100 and TFBGA100 packages supports up to 8/16 data
line wide static memory, in addition to dynamic memories, such as, SDRAM (2 banks
only) with an SDRAM clock of up to 100 MHz.
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
76 of 169
NXP [ NXP ]
