LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
[2] Tcy(clk) = 1/EMC_CLK (see UM10912 LPC546xx manual).
[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM10912
LPC546xx manual).
EMC_Ax
RD
WR
1
1
EMC_CSx
EMC_OE
WR
8
RD
8
RD
2
RD
4
RD
7
WR
WR
WR
11
9
10
EMC_BLSx
EMC_WE
RD
5a
RD
5b
WR
2
WR
12
RD
RD
5
6
EMC_Dx
EOW
EOR
aaa-026103
Fig 24. External static memory read/write access (PB = 0)
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
108 of 169
NXP [ NXP ]
