Philips Semiconductors
Product specification
Dual binary counter
DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP
0
) and an active LOW clock input (CP
1
), buffered
outputs from all four bit positions (O
0
to O
3
) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP
0
input if CP
1
is HIGH or the HIGH to
HEF4520B
MSI
LOW transition of the CP
1
input if CP
0
is low. Either CP
0
or
CP
1
may be used as the clock input to the counter and the
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O
0
to O
3
= LOW)
independent of CP
0
, CP
1
.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.2 Pinning diagram.
HEF4520BP(N):
HEF4520BD(F):
HEF4520BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic (SOT109-1)
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
CP
0A
, CP
0B
CP
1A
, CP
1B
MR
A
, MR
B
O
0A
to O
3A
O
0B
to O
3B
clock inputs (L to H triggered)
clock inputs (H to L triggered)
master reset inputs
outputs
outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
PHILIPS [ NXP SEMICONDUCTORS ]
