Philips Semiconductors
Product specification
Programmable divide-by-n counter
DESCRIPTION
The HEF4059B is a divide-by-n counter which can be
programmed to divide an input frequency by any number
n
from 3 to 15 999. The output signal is a one clock-cycle
HEF4059B
LSI
wide pulse and occurs at a rate equal to the input
frequency divided by
n.
The single output (O) has TTL
drive capability. The down counter is preset by means of
16 jam inputs (J1 to J16); continued on next page.
Fig.1 Functional block diagram.
PINNING
CP
K
a
, K
b
, K
c
J
1
to J
16
EL
O
clock input
mode select inputs
programmable jam inputs (BCD)
latch enable input
divide-by-n output
HEF4059BP(N): 24-lead DIL; plastic (SOT101-1)
Fig.2 Pinning diagram.
HEF4059BD(F):
HEF4059BT(D):
FAMILY DATA, I
DD
LIMITS category LSI
See Family Specifications
24-lead DIL; ceramic (cerdip) (SOT94)
24-lead SO; plastic (SOT137-1)
( ): Package Designator North America
January 1995
2
PHILIPS [ NXP SEMICONDUCTORS ]
