NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
output compare or PWM modes, the interrupt flag is set each time the main timer counter
matches the value in the 16-bit channel value register. See Section 7 "Reset, interrupts
and system configuration" for absolute interrupt vector addresses, priority, and local
interrupt mask control bits.
For each interrupt source in the TPM1, a flag bit is set on recognition of the interrupt
condition such as timer overflow, channel input capture, or output compare events.
This flag may be read (polled) by software to verify that the action has occurred, or
an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt
generation. While the interrupt enable bit is set, a static interrupt will be generated
whenever the associated interrupt flag equals 1. It is the responsibility of user software to
perform a sequence of steps to clear the interrupt flag before returning from the interrupt
service routine.
11.6.1 Clearing timer interrupt flags
TPM1 interrupt flags are cleared by a two-step process that includes a read of the flag
bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between
these two steps, the sequence is reset and the interrupt flag remains set after the second
step to avoid the possibility of missing the new event.
11.6.2 Timer overflow interrupt description
The conditions that cause TOF to become set depend on the counting mode (up or
up/down). In up-counting mode, the 16-bit timer counter counts from 0x0000 through
0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at
the transition from the value set in the modulus register to 0x0000. When the counter
is operating in up-/down-counting mode, the TOF flag gets set as the counter changes
direction at the transition from the value set in the modulus register and the next lower
count value. This corresponds to the end of a PWM period. (The 0x0000 count value
corresponds to the center of a period.)
11.6.3 Channel event interrupt description
The meaning of channel interrupts depends on the current mode of the channel (input
capture, output compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control
bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers
an input capture event. When the selected edge is detected, the interrupt flag is set. The
flag is cleared by the two-step sequence described in Section 11.6.1 "Clearing timer
interrupt flags".
When a channel is configured as an output compare channel, the interrupt flag is set
each time the main timer counter matches the 16-bit value in the channel value register.
The flag is cleared by the two-step sequence described in Section 11.6.1 "Clearing timer
interrupt flags".
11.6.4 PWM end-of-duty-cycle events
For channels that are configured for PWM operation, there are two possibilities:
FXTH87ERM
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Reference manual
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