NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
not necessary). This is not a significant limitation because the resulting period is much
longer than required for normal applications.
TPM1MODH:TPM1MODL = 0x0000 is a special case that should not be used with
center-aligned PWM mode. When CPWMS = 0, this case corresponds to the counter
running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a
valid match to the modulus register somewhere other than at 0x0000 in order to change
directions from up-counting to down-counting.
Figure 20 shows the output compare value in the TPM1 channel registers (multiplied by
2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the
compare match while counting up forces the CPWM output signal low and a compare
match while counting down forces the output high. The counter counts up until it reaches
the modulo setting in TPM1MODH:TPM1MODL, then counts down until it reaches zero.
This sets the period equal to two times TPM1MODH:TPM1MODL.
COUNT = 0
Output compare
(count down)
Output compare
(count up)
Count = TPMMODH:TPMMODL
TPM1CHn
Count = TPMMODH:TPMMODL
Pulse width 2x
Period 2x
aaa-028014
Figure 20.ꢀCPWM period and pulse width (ELSnA = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs
because fewer I/O pin transitions are lined up at the same system clock edge. This type
of PWM is also required for some types of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers
are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse
widths. Writes to any of the registers, TPM1MODH, TPM1MODL, TPM1CnVH, and
TPM1CnVL, actually write to buffer registers. Values are transferred to the corresponding
timer channel registers only after both 8-bit bytes of a 16-bit register have been written
and the timer counter overflows (reverses direction from up-counting to down- counting
at the end of the terminal count in the modulus register). This TPM1CNT overflow
requirement only applies to PWM channels, not output compares.
Optionally, when TPM1CNTH:TPM1CNTL = TPM1MODH:TPM1MODL, the TPM1 can
generate a TOF interrupt at the end of this count. The user can choose to reload any
number of the PWM buffers, and they will all update simultaneously at the start of a new
period.
Writing to TPM1SC cancels any values written to TPM1MODH and/or TPM1MODL and
resets the coherency mechanism for the modulo registers. Writing to TPM1C0SC cancels
any values written to the channel value registers and resets the coherency mechanism
for TPM1C0VH:TPM1C0VL.
11.6 TPM1 interrupts
The TPM1 generates an optional interrupt for the main counter overflow and an interrupt
for each channel. The meaning of channel interrupts depends on the mode of operation
for each channel. If the channel is configured for input capture, the interrupt flag is set
each time the selected input capture edge is recognized. If the channel is configured for
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
97 / 183
NXP [ NXP ]
