NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
For compatibility with the M68HC08, the H register is not automatically saved and
restored. It is good programming practice to push H onto the stack at the start of the
interrupt service routine (ISR) and restore it just before the RTI that is used to return from
the ISR.
7.5.1 Interrupt stack frame
Table 29 shows the contents and organization of a stack frame. Before the interrupt, the
stack pointer (SP) points at the next available byte location on the stack. The current
values of CPU registers are stored on the stack starting with the low-order byte of the
program counter (PCL) and ending with the CCR. After stacking, the SP points at the
next available location on the stack which is the address that is one less than the address
where the CCR was saved. The PC value that is stacked is the address of the instruction
in the main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in
reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by
reading three bytes of program information, starting from the PC address just recovered
from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning
from the ISR. Typically, the flag should be cleared at the beginning of the ISR so that
if another interrupt is generated by this same source, it will be registered so it can be
serviced after completion of the current ISR.
Towards LOWER addresses
Unstacking
order
7
0
SP after
interrupt stacking
1
2
3
4
5
5
4
3
2
1
Condition code register (CCR)
Accumulator
Index register* (low byte x)
Program counter high
Program counter low
SP before
the interrupt
Stacking
order
Towards HIGHER addresses
* High byte (H) of index register is not automatically stacked.
aaa-028000
Figure 12.ꢀInterrupt stack frame
7.5.2 Vector summary
Table 31 provides a summary of all interrupt sources. Higher-priority sources are located
toward the bottom of the table (at the higher vector addresses). All of these vectors are
a 2-byte address that the firmware uses as the destination address. This allows the
firmware to intercept all vectors and add additional processing as needed. The additional
process latency for each interrupt will be described in Section 16 "Firmware".
Therefore, the high-order byte of the address for the user’s interrupt service routine is
located at the lower address in the vector address column, and the low-order byte of
the address for the interrupt service routine is located at the higher address. When an
interrupt condition occurs, an associated flag bit becomes set. If the associated local
interrupt enable is set, an interrupt request is sent to the CPU. Within the CPU, if the
global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction,
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
39 / 183
NXP [ NXP ]
