NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
COPT
1
COP
COP Overflow Time
Clock
Source
COPCLKS
Overflow
(ms, nominal)
Count
2
0
1:1
1:0
0:1
0:0
(0.5 MHz) (1 MHz)
(2 MHz)
(4MHz)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bus Clock
Bus Clock
Bus Clock
Bus Clock
Bus Clock
Bus Clock
Bus Clock
Bus Clock
213
214
215
216
217
218
219
219
16.384
32.768
65.536
131.072
8.192
16.384
32.768
65.536
4.096
8.192
2.048
4.096
16.384
32.768
65.536
8.192
16.384
32.768
65.536
262.144 131.072
524.288 262.144 131.072
1048.576 524.288 262.144 131.072
1048.576 524.288 262.144 131.072
After any reset, the COP timer is enabled. This provides a reliable way to detect code
that is not executing as intended. If the COP watchdog is not used in an application, it
can be disabled by clearing the COPE bit in the write-once SIMOPT1 register. Even if
the application will use the reset default settings in COPE, COPCLKS and COPT[2:0],
the user should still write to write- once SIMOPT1 during reset initialization to lock in the
settings. That way, they cannot be changed accidentally if the application program gets
lost.
The write to SRS that services (clears) the COP timer should not be placed in an
interrupt service routine (ISR) because the ISR could continue to be executed
periodically even if the main application program fails. When the MCU is in ACTIVE
BACKGROUND DEBUG mode, or either Stop1 or Stop4 modes, the COP timer is
temporarily disabled. If enabled, the COP timer is reset at the time entering Stop1 and
Stop4 modes, and will restart after 3 cycles of the selected clock source upon exiting; RTI
may be used as a substitute.
7.4 SIM test register (SIMTST)
The output of the temperature monitor is available using the SIM Test register as shown
in Table 29.
Table 29.ꢀSIM test register (SIMTST) (address $180F)
Bit
R
7
6
5
TRH
1
4
3
2
1
0
TRO
W
Reset
0
0
1
1
0
0
1
= Reserved
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
37 / 183
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