NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Direct page registers are located within the first 256 locations in the memory map, so
they are accessible with efficient direct addressing mode instructions, which requires
only the lower byte of the address. Bit manipulation instructions can be used to access
any bit in any direct-page register. Table 7 is a summary of all user-accessible direct-
page registers and control bits. Those related to the TPMS application and modules are
described in detail in this specification.
Table 7.ꢀMCU direct page register summary
Cells that are not associated with named bits are shaded
• Shaded cell with a 0 indicate an unused bit that always reads as 0
• Shaded cells not containing a value indicate unused or reserved bit locations that could read as 1s or 0s
Address
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Register Name
PTAD
Bit 7
6
5
4
3
2
1
Bit 0
PTAD[4:0]
PTAPE
PTAPE[3:0]
Reserved
PTADD
PTADD[3:0]
PTBD
PTBD[1:0]
PTBPE
PTBPE[1:0]
Reserved
PTBDD
PTBDD[1:0]
Reserved
Reserved
Reserved
Reserved
KBISC
0
0
0
0
KBF
KBACK
KBIE
KBIMOD
KBIPE
KBIPE[3:0]
KBIES
KBEDG[3:0]
Reserved
TPM1SC
TPM1CNTH
TPM1CNTL
TPM1MODH
TPM1MODL
TPM1C0SC
TPM1C0VH
TPM1C0VL
TPM1C1SC
TPM1C1VH
TPM1C1VL
Reserved
PWUDIV
PWUCS0
PWUCS1
PWUS
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit [15:8]
Bit [7:0]
Bit [15:8]
Bit [7:0]
CH0F
CH1F
CH0IE
CH1IE
MS0B
MS1B
MS0A
ELS0B
ELS0A
ELS1A
0
0
0
0
Bit [15:8]
Bit [7:0]
MS1A
ELS1B
Bit [15:8]
Bit [7:0]
WDIV[5:0]
WUF
PRF
WUFAK
PRFAK
0
WUT[5:0]
PRST[5:0]
CSTAT[5:0]
PSEL
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
19 / 183
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