NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Figure 51 shows the host receiving a logic 1 from the target HCS08 MCU. Because the
host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-
generated falling edge on BKGD/PTA4 to the perceived start of the bit time in the target
MCU. The host holds the BKGD/PTA4 pin low long enough for the target to recognize it
(at least two target BDC cycles). The host must release the low drive before the target
MCU drives a brief active-high speedup pulse seven cycles after the perceived start of
the bit time. The host should sample the bit level about 10 cycles after it started the bit
time.
BDC clock
(target MCU)
Host drive to
High-impedance
BKGD/PTA4 pin
Target MCU
speedup pulse
High-impedance
R-C rise
High-impedance
Perceived start
of bit time
BKGD/PTA4 pin
10 cycles
10 cycles
Earliest start of next bit
Host samples BKGD PTA4 pin
aaa-028044
Figure 51.ꢀBDC target-to-host serial bit timing (Logic 1)
Figure 52 shows the host receiving a logic 0 from the target HCS08 MCU. Because the
host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-
generated falling edge on BKGD/PTA4 to the start of the bit time as perceived by the
target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD/PTA4 pin low for 13 BDC
clock cycles, then briefly drives it high to speed up the rising edge. The host samples the
bit level about 10 cycles after starting the bit time.
BDC clock
(target MCU)
Host drive to
High-impedance
BKGD/PTA4 pin
Speedup
Target MCU
drive and
pulse
speedup pulse
Perceived start
of bit time
BKGD/PTA4 pin
10 cycles
Earliest start of next bit
10 cycles
Host samples BKGD PTA4 pin
aaa-028045
Figure 52.ꢀBDM target-to-host serial bit timing (Logic 0)
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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