NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
When no debugger pod is connected to the 6-pin BDM interface connector, the internal
pullup on BKGD/PTA4 chooses normal operating mode. When a debug pod is connected
to BKGD/PTA4 it is possible to force the MCU into ACTIVE BACKGROUND mode after
reset. The specific conditions for forcing ACTIVE BACKGROUND depend upon the
HCS08 derivative (refer to the introduction to this Development Support section). It is not
necessary to reset the target MCU to communicate with it through the BACKGROUND
DEBUG interface.
17.2.2 Communication details
The BDC serial interface requires the external controller to generate a falling edge on the
BKGD/PTA4 pin to indicate the start of each bit time. The external controller provides this
falling edge whether data is transmitted or received.
BKGD/PTA4 is a pseudo-open-drain pin that can be driven either by an external
controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit
(nominal speed). The interface times out if 512 BDC clock cycles occur between falling
edges from the host. Any BDC command that was in progress when this timeout occurs
is aborted without affecting the memory or operating mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC
communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the
user to select the BDC clock source. The BDC clock source can either be the bus or the
alternate BDC clock source.
The BKGD/PTA4 pin can receive a high or low level or transmit a high or low level. The
following diagrams show timing for each of these cases. Interface timing is synchronous
to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
Figure 50 shows an external host transmitting a logic 1 or 0 to the BKGD/PTA4 pin of
a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle
delay from the host-generated falling edge to where the target perceives the beginning
of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the
BKGD/PTA4 pin. Typically, the host actively drives the pseudo-open-drain BKGD/PTA4
pin during host-to-target transmissions to speed up rising edges. Because the target
does not drive the BKGD/PTA4 pin during the host-to-target transmission period, there is
no need to treat the line as an open-drain signal during this period.
BDC clock
(target MCU)
Host
transmit 1
Host
transmit 0
10 cycles
Earliest start of next bit
Target senses bit level
Synchronization
uncertinity
Perceived start
of bit time
aaa-028043
Figure 50.ꢀBDC host-to-target serial bit timing
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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