NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
to trace one user instruction at a time, or GO to the user program from ACTIVE
BACKGROUND mode.
• Non-intrusive commands can be executed at any time even while the user’s program is
running. Non-intrusive commands allow a user to read or write MCU memory locations
or access status and control registers within the BACKGROUND DEBUG controller.
Typically, a relatively simple interface pod is used to translate commands from a
host computer into commands for the custom serial interface to the single-wire
BACKGROUND DEBUG system. Depending on the development tool vendor, this
interface pod may use a standard RS-232 serial port, a parallel printer port, or some
other type of communications such as a universal serial bus (USB) to communicate
between the host PC and the pod. The pod typically connects to the target system with
ground, the BKGD/PTA4 pin, RESET, and sometimes VDD. An open-drain connection to
reset allows the host to force a target system reset, which is useful to regain control of a
lost target system or to control startup of a target system before the on-chip nonvolatile
memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However,
if the pod is powered separately, it can be connected to a running target system without
forcing a target system reset or otherwise disturbing the running application program.
1
2
BKGD
NO CONNECT 3
NO CONNECT
GND
4 RESET
VDD
6
5
aaa-028042
Figure 49.ꢀBDM tool connector
17.2.1 BKGD/PTA4 pin description
BKGD/PTA4 is the single-wire BACKGROUND DEBUG interface pin. The primary
function of this pin is for bidirectional serial communication of ACTIVE BACKGROUND
mode commands and data. During reset, this pin is used to select between starting
in ACTIVE BACKGROUND mode or starting the user’s application program. This
pin is also used to request a timed sync response pulse to allow a host development
tool to determine the correct clock frequency for BACKGROUND DEBUG serial
communications.
BDC serial communications use a custom serial protocol first introduced on the
M68HC12 Family of microcontrollers. This protocol assumes the host knows the
communication clock rate that is determined by the target BDC clock rate. All
communication is initiated and controlled by the host that drives a high-to-low edge to
signal the beginning of each bit time. Commands and data are sent most significant
bit first (MSB first). For a detailed description of the communications protocol, refer to
Section 17.2.2 "Communication details".
If a host is attempting to communicate with a target MCU that has an unknown BDC
clock rate, a SYNC command may be sent to the target MCU to request a timed sync
response signal from which the host can determine the correct communication speed.
BKGD/PTA4 is a pseudo-open-drain pin and there is an on-chip pullup so no external
pullup resistor is required. Unlike typical open-drain pins, the external RC time constant
on this pin, which is influenced by external capacitance, plays almost no role in signal
rise time. The custom protocol provides for brief, actively driven speedup pulses to force
rapid rise times on this pin without risking harmful drive level conflicts. Refer to Figure 48,
for more detail.
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
164 / 183
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