NXP Semiconductors
BSS84
P-channel enhancement mode vertical DMOS transistor
1.2
V
GSth
V
GSth(25°C)
1.0
mld195
80
C
(pF)
60
mld191
40
C
iss
20
C
oss
C
rss
0.6
−50
0
0
50
100
T
j
(°C)
150
0
−10
−20
−30
0.8
V
DS
(V)
I
D
=
−1
mA; V
DS
= V
GS
V
GS
=
0
V; f = 1 MHz
Fig 8.
Gate-source threshold voltage as a function of
junction temperature
Fig 9.
Input, output and reverse transfer
capacitances as a function of drain-source
voltage; typical values
8. Test information
10 %
V
DS
=
−40
V
INPUT
90 %
10 %
0V
−10
V
50
Ω
OUTPUT
I
D
90 %
t
on
mld189
t
off
mbb690
Fig 10. Switching time test circuit
Fig 11. Input and output waveforms
BSS84_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 16 December 2008
7 of 11
PHILIPS [ NXP SEMICONDUCTORS ]
