欢迎访问ic37.com |
会员登录 免费注册
发布采购

74LVC245APW 参数 Datasheet PDF下载

74LVC245APW图片预览
型号: 74LVC245APW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路总线收发器方向引脚可承受5V的输入/输出(三态) [Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state)]
分类和应用: 总线驱动器总线收发器逻辑集成电路光电二极管PC
文件页数/大小: 12 页 / 307 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
 浏览型号74LVC245APW的Datasheet PDF文件第2页浏览型号74LVC245APW的Datasheet PDF文件第3页浏览型号74LVC245APW的Datasheet PDF文件第4页浏览型号74LVC245APW的Datasheet PDF文件第5页浏览型号74LVC245APW的Datasheet PDF文件第6页浏览型号74LVC245APW的Datasheet PDF文件第7页浏览型号74LVC245APW的Datasheet PDF文件第8页浏览型号74LVC245APW的Datasheet PDF文件第9页  
74LVC245A
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(NOT INVERTED) HIGH PERFORMANCE
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED: t
PD
= 6.3ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC245AMTR
74LVC245ATTR
DESCRIPTION
The 74LVC245A is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for 1.65 to 3.6
V
CC
operations and low power and low noise
applications.
This IC is intended for two-way asynchronous
communication between data buses and the
Figure 1: Pin Connection And IEC Logic Symbols
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
July 2004
.
Rev. 4
1/12