Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
FEATURES
•
8-bit serial input
•
8-bit serial or parallel output
•
Storage register with 3-state outputs
•
Shift register with direct clear
•
100 MHz (typical) shift out frequency
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
APPLICATIONS
•
Serial-to-parallel data conversion
•
Remote control holding register.
DESCRIPTION
74HC595; 74HCT595
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT595 is an 8-stage serial shift register with a
storage register and 3-state outputs. The shift register and
storage register have separate clocks.
Data is shifted on the positive-going transitions of the
SH_CP input. The data in each register is transferred to
the storage register on a positive-going transition of the
ST_CP input. If both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided
with asynchronous reset (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state
bus driver outputs. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
SH_CP to Q7’
SH_CP to Qn
MR to Q7’
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC595 the condition is V
I
= GND to V
CC
.
For 74HCT595 the condition is V
I
= GND to V
CC
−
1.5 V.
2003 Jun 25
2
maximum clock frequency SH_CP and ST_CP
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
74HC
C
L
= 50 pF; V
CC
= 4.5 V
19
20
100
100
3.5
115
25
24
52
57
3.5
130
ns
ns
ns
MHz
pF
pF
74HCT
UNIT
PHILIPS [ NXP SEMICONDUCTORS ]
