NXP Semiconductors
74HC11; 74HCT11
Triple 3-input AND gate
4. Functional diagram
1
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
mna793
2
1Y
12
13
3
2Y
6
4
5
&
12
&
6
A
3Y
8
9
10
11
mna792
&
8
B
C
Y
mna794
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
74HC11
74 HCT11
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
001aal407
14 V
CC
13 1C
1A
12 1Y
11 3C
10 3B
9
8
3A
3Y
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
74HC11
74HCT11
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9
8
3A
3Y
001aal408
Fig 4.
Pin configuration DIP14 and SO14
Fig 5.
Pin configuration (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
1C, 2C, 3C
1Y, 2Y, 3Y
V
CC
Pin description
Pin
1, 3, 9
2, 4, 10
7
13, 5, 11
12, 6, 8
14
Description
data input
data input
ground (0 V)
data input
data output
supply voltage
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
2 of 15
PHILIPS [ NXP SEMICONDUCTORS ]
