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M58LT256JST 参数 Datasheet PDF下载

M58LT256JST图片预览
型号: M58LT256JST
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆位( Mb的16 】 16 ,多银行,多层次,突发) 1.8 V电源供电,安全闪存 [256 Mbit (16 Mb 】 16, multiple bank, multilevel, burst) 1.8 V supply, secure Flash memories]
分类和应用: 闪存
文件页数/大小: 108 页 / 1965 K
品牌: NUMONYX [ NUMONYX B.V ]
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Description  
M58LT256JST, M58LT256JSB  
1
Description  
The M58LT256JST/B are 256 Mbit (16 Mbit x 16) non-volatile secure Flash memories. They  
may be erased electrically at block level and programmed in-system on a word-by-word  
basis using a 1.7 V to 2.0 V V supply for the circuitry and a 2.7 V to 3.6 V V  
supply for  
DD  
DDQ  
the input/output pins. An optional 9 V V power supply is provided to speed up factory  
PP  
programming.  
The devices feature an asymmetrical block architecture. The M58LT256JST/B have an array  
of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16  
main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16  
KWords and 15 main blocks of 64 KWords.  
The multiple bank architecture allows dual operations. While programming or erasing in one  
bank, read operations are possible in other banks. Only one bank at a time is allowed to be  
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.  
The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3.  
The parameter blocks are located at the top of the memory address space for the  
M58LT256JST, and at the bottom for the M58LT256JSB.  
Each block can be erased separately. Erase can be suspended to perform a program or  
read operation in any other block, and then resumed. Program can be suspended to read  
data at any memory location except for the one being programmed, and then resumed.  
Each block can be programmed and erased over 100 000 cycles using the supply voltage  
V
. There is a buffer enhanced factory programming command available to speed up  
DD  
programming.  
Program and erase commands are written to the command interface of the memory. An  
internal Program/Erase Controller manages the timings necessary for program and erase  
operations. The end of a program or erase operation can be detected and any error  
conditions identified in the Status Register. The command set required to control the  
memory is consistent with JEDEC standards.  
The device supports synchronous burst read and asynchronous read from all blocks of the  
memory array. At power-up the device is configured for asynchronous read. In synchronous  
burst read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The  
synchronous burst read operation can be suspended and resumed.  
The device features an automatic standby mode. When the bus is inactive during  
asynchronous read operations, the device automatically switches to the automatic standby  
mode. In this condition the power consumption is reduced to the standby value and the  
outputs are still driven.  
The M58LT256JST/B features an instant, individual block protection scheme that allows any  
block to be protected or unprotected with no latency, enabling instant code and data  
protection. They can be protected individually preventing any accidental programming or  
erasure. There is an additional hardware protection against program and erase. When  
V
V  
all blocks are protected against program or erase. All blocks are protected at  
PP  
PPLK  
power-up.  
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