M58LT128HST, M58LT128HSB
Description
1
Description
The M58LT128HST/B are 128 Mbit (8 Mbit x 16) non-volatile secure Flash memories. They
may be erased electrically at block level and programmed in system on a word-by-word
basis using a 1.7 V to 2.0 V V supply for the circuitry and a 2.7 V to 3.6 V V
supply for
DD
DDQ
the Input/Output pins. An optional 9 V V power supply is provided to accelerate factory
PP
programming.
The devices feature an asymmetrical block architecture, with an array of 131 blocks, divided
into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one
parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64
Kwords.
The multiple bank architecture allows dual operations, while programming or erasing in one
bank, Read operations are possible in other banks. Only one bank at a time is allowed to be
in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3.
The parameter blocks are located at the top of the memory address space for the
M58LT128HST, and at the bottom for the M58LT128HSB.
Each block can be erased separately. Erase can be suspended to perform a program or
read operation in any other block, and then resumed. Program can be suspended to read
data at any memory location except for the one being programmed, and then resumed.
Each block can be programmed and erased over 100,000 cycles using the supply voltage
V
. There is a buffer-enhanced factory programming command available to accelerate
DD
programming.
Program And Erase Commands Are Written To The command interface of the memory. An
internal Program/Erase Controller manages the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports Synchronous Burst Read and Asynchronous Read from all blocks of
the memory array; at power-up the device is configured for Asynchronous Read. In
Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to
52 MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
The M58LT128HST/B features an instant, individual block protection scheme that allows any
block to be protected or unprotected with no latency, enabling instant code and data
protection. They can be protected individually preventing any accidental programming or
erasure. There is an additional hardware protection against program and erase. When V
≤
PP
V
all blocks are protected against program or erase. All blocks are protected at power-
PPLK
up.
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NUMONYX [ NUMONYX B.V ]
