Read modes
M58LT128HST, M58LT128HSB
7.2.1
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other
higher priority devices. It can be suspended during the initial access latency time (before
data is output) or after the device has output data. When the Synchronous Burst Read
operation is suspended, internal array sensing continues and any previously latched internal
data is retained. A burst sequence can be suspended and resumed as often as required as
long as the operating conditions of the device are met.
A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at V or at V , and Output Enable, G, goes High.
IH
IL
When Output Enable, G, becomes Low again and the Clock signal restarts, the
Synchronous Burst Read operation resumes exactly where it stopped.
WAIT reverts to high-impedance whenever Chip Enable, E, or Output Enable, G, goes High.
See Table 23: Synchronous Read AC characteristics and Figure 13: Synchronous Burst
Read Suspend AC waveforms for details.
7.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations
except that the memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,
Block Protection Status, Configuration Register Status or Protection Register. When the
addressed bank is in Read CFI, Read Status Register, or Read Electronic Signature mode,
the WAIT signal is asserted during the X-latency, the WAIT state, and at the end of a 4-, 8-
and 16-word burst. It is only de-asserted when output data are valid.
See Table 23: Synchronous Read AC characteristics and Figure 12: Single Synchronous
Read AC waveforms for details.
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