M58LT128HST, M58LT128HSB
Configuration Register
6.7
Valid Clock Edge bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
Synchronous Read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling
edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the
rising edge of the Clock is the active edge.
6.8
Wrap Burst bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous Burst
reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary
(no wrap).
When the Wrap Burst bit is Low (set to ‘0’) the Burst Read wraps. When it is High (set to ‘1’)
the Burst Read does not wrap.
6.9
Burst length bits (CR2-CR0)
The Burst Length bits are used to set the number of words to be output during a
Synchronous Burst Read operation as result of a single address latch cycle.
They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are
read sequentially. In Continuous Burst mode the burst sequence can cross bank
boundaries.
In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address,
the device asserts the WAIT signal to indicate that a delay is necessary before the data is
output.
If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is
asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first
16-word boundary. This indicates that the device needs an internal delay to read the
successive words in the array. WAIT is only asserted once during a continuous burst access.
See also Table 12: Burst type definition.
CR14, CR5 and CR4 are reserved for future use.
39/110
NUMONYX [ NUMONYX B.V ]
