M58LT128HST, M58LT128HSB
Bus operations
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for
a summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at V to perform a Read operation. The Chip Enable input is used to
IL
enable the device. Output Enable is used to gate data onto the output. The data read
depends on the previous command written to the memory (see Command Interface
section). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 22 and 23 Read AC
Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write commands to the memory or latch input data to be programmed.
A Bus Write operation is initiated when Chip Enable and Write Enable are at V with Output
IL
Enable at V . Commands, input data and addresses are latched on the rising edge of Write
IH
Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the
write operation by toggling Latch Enable (when Chip Enable is at V ). The Latch Enable
IL
must be tied to V during the Bus Write operation.
IH
See Figures 15 and 16, Write AC waveforms, and Tables 24 and 25, Write AC
characteristics, for details of the timing requirements.
3.3
3.4
Address Latch
Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must
be at V during Address Latch operations. The addresses are latched on the rising edge of
IL
Latch Enable.
Output Disable
The outputs are high impedance when the Output Enable is at V .
IH
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NUMONYX [ NUMONYX B.V ]
